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SPRA921
4 TMS320C6713 Digital Signal Processor Optimized for High Performance Multichannel Audio Systems
TMS320C6713
digital
signal
processor
EMIF
Host
processor
ROM
Serially
controlled
interface
devices
HPI IIC IIC
GPIO
SDRAM
Directly
connected to
other system
components
McASP
port 0
port 1
McASP
Multiple serial
output streams
(D/A converters,
DIT/SPDIF line
converters)
Multiple serial
input streams
(A/D converters,
DIR/SPDIF
receivers)
McASP
port 0
McASP
port 1
Figure 2. Generalized High Performance Multichannel Audio System
McBSP0
McBSP1
McASP0
McASP1
32
EMIF
I2C1
I2C0
Timer 1
Timer 0
32
HPI
GRO
Enhanced
DMA
controller
(16
L2Cache/
memory
4 banks
64K
bytes
total
(up to
L2
memory
192K
bytes
channel)
Clock generator
oscillator and PLL
x4 through x25
multiplier
/1 through /32
dividers
4–way)
L1D cache 2–way
set associative
4K bytes
direct mapped
4K bytes total
L1P cache
C67x CPU
Power–
down
logic
C6713 digital signal processor
Pin multiplexing
Figure 3. TMS3206713 CPU and Peripheral Connectivity.