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Specifications
ARM DUI 0125A
© Copyright ARM Limited 1999. All rights reserved.
B-3
B.2 Timing specification
Table B-2 provides the operating timing characteristics for the system bus interface
signals.
Table B-2 Core module timing (preliminary)
Symbol Description Min Max Units
F
MAX
Operating frequency - 25 MHz
T
CH
Clock HIGH 19 - ns
T
CL
Clock LOW 19 - ns
T
CO
Clock to output – signals generated and
sampled on same clock edge
-16.0ns
Clock to output – signals generated and
sampled on different clock edge
-8.0ns
T
IC
Input to clock – signals generated and
sampled on same clock edge
-8.0ns
Input to clock – signals generated and
sampled on different clock edge
-4.0ns
T
BPD
Motherboard propagation delay (for
guidance only)
-1.0ns
T
SKEW
Motherboard clock skew for guidance
only)
-1.0ns