Index
Index-8
emulator
cable pod E-5
connection to target system, JTAG mechanical
dimensions E-14 to E-25
designing the JTAG cable E-1
emulation pins E-20
pod interface E-5
pod timings E-6
signal buffering E-10 to E-13
target cable, header design E-2 to E-3
enhanced instructions B-5
error conditions
asynchronous serial port
framing error (FE bit) 10-11
overrun (OE bit) 10-11
synchronous serial port
burst mode 9-29
continuous mode 9-29
examples of ’C2xx program code C-1 to C-24
external access active strobe (STRB
) 4-3
external address bus (A0–A15)
definition 4-3
shown in figure 4-6, 4-10, 4-13, 4-15, 4-26
external data bus (D0–D15)
definition 4-3
shown in figure 4-6, 4-10, 4-13, 4-15, 4-26
external device ready pin (READY)
definition 4-4
generating wait states with 8-14
external interfacing, diagrams 4-6, 4-10, 4-13, 4-26
external oscillator, using (diagram) 8-5
F
FE bit 10-11
features summary 1-6
FIFO buffers, introduction 9-5
FINT2 bit 5-26
FINT3 bit 5-26
flag bits
I/O status register (IOSR) 10-10
interrupt control register (ICR) 5-18
interrupt flag register (IFR) 5-18
flash memory (on-chip), introduction 2-9
flow charts
interrupt operation
maskable interrupts 5-20
nonmaskable interrupts 5-29
requesting INT2
and INT3 5-18
TMS320 ROM code submittal D-2
4-level pipeline operation 5-7
14-pin connector, dimensions E-15
14-pin header
header signals E-2
JTAG E-2
FR1 and FR0 bits 9-10
frame synchronization mode (FSM bit) 9-11
framing error (FE bit) 10-11
FREE bit
asynchronous serial port 10-7
synchronous serial port 9-8
timer 8-11
FSM bit 9-11
FSR pin 9-4
FSX pin 9-4
FT1 and FT0 bits 9-9
G
general-purpose I/O pins 8-17 to 8-20
input
BIO 8-17 to 8-18
IO0–IO3 10-15 to 10-16
output
IO0–IO3 10-15 to 10-16
XF 8-18
generating executable files, figure C-2
generating wait states with 8-14
generators (on-chip)
baud-rate generator 10-4
clock generator 8-4 to 8-6
’C209 clock options 11-14 to 11-18
wait-state generator 8-14 to 8-16
’C209 11-16 to 11-18
global data memory 4-11
configuration 4-11
external interfacing 4-12
global memory allocation register (GREG) 4-11
GREG (global memory allocation register) 4-11
