Design Guide 19
Intel
®
31244 PCI-X to Serial ATA Controller
Intel
®
31244 PCI-X to Serial ATA Controller Package
Table 4. PCI-X Bus Pin Descriptions (Sheet 1 of 2)
Name Description
CAP2, CAP3
Analog: An external 0.015 µF (+/- 10%) capacitor is connected between these pins to set
the PCI PLL loop filter response.
P_ACK64#
BIDIRECTIONAL - LVTTL: Indicates that the device has positively decoded its address as
the target of the current access and the target is willing to transfer data using the full 64-bit
data bus.
P_AD[63:0]
BIDIRECTIONAL - LVTTL PCI Address and Data: The address and data lines are
multiplexed on these pins. A bus transaction consists of an address phase followed by one
or more data phases. P_AD[63:56] contains the most significant byte and P_AD[7:0] contain
the least significant byte.
P_C/BE[7:0]#
BIDIRECTIONAL - LVTTL: Command and Byte Enable. The bus command and byte enable
signals are multiplexed on these pins. During the address phase, the P_CBE# lines define
the bus command. During the data phase, the P_CBE# lines are used as Byte Enables. The
Byte Enables are valid for the entire data phase and determine which byte lanes carry
meaningful data.
P_CLK All PCI bus signals are referenced to this clock.
P_DEVSEL#
BIDIRECTIONAL - LVTTL with Pull-Up Resistor: Device Select. This signal is asserted by
the target once it has detected its address. As a bus master, the P_DEVSEL# is an input
signal to the Intel
®
31244 PCI-X to serial ATA controller indicating whether any device on the
bus has been selected. As a bus slave, the GD31244 asserts P_DEVSEL# to indicate that it
has decoded its address as the target of the current transaction.
P_FRAME#
BIDIRECTIONAL - LVTTL with Pull-Up Resistor: Cycle Frame. This signal is driven by the
current master to indicate the beginning and duration of a transaction. P_FRAME# is
asserted to indicate the start of a transaction and de-asserted during the final data phase.
P_GNT#
INPUT - LVTTL. Grant: This signal is asserted by the bus arbiter and indicates to the
GD31244 that access to the bus has been granted. This is a point-to-point signal and every
master has its own GNT#.
P_IDSEL
INPUT - LVTTL. Initialization Device Select: This signal is used as a chip select during
PCI-X configuration read and write transactions. This signal is provided by the host in PCI-X
systems.
P_INTA#
OUTPUT - Open Drain Interrupt A: This signal is used to request an interrupt by the
GD31244. This is an active low, level triggered interrupt signal.
P_IRDY#
BIDIRECTIONAL - LVTTL with Pull-Up Resistor: Initiator Ready. This signal indicates the
bus master ability to complete the current data phase and is used in conjunction with the
target ready (P_TRDY#) signal. A data phase is completed on any clock cycle where both
P_IRDY# and P_TRDY# are asserted LOW.
P_PAR
BIDIRECTIONAL - LVTTL: Parity. Parity is even across P_AD[31:0] and P_CBE[3:0]# lines.
It is stable and valid one clock after the address phase. For data phases, P_PAR is stable
and valid one clock after either P_IRDY# is asserted on a write or P_TRDY# is asserted on
a read.Once P_PAR is valid, it remains valid until one clock after the completion of the
current data phase. The master drives P_PAR for address and write data phases; and the
target, for read data phases.
P_PAR64
BIDIRECTIONAL - LVTTL: Parity for 64-bit Accesses. Parity is even across P_AD[63:0] and
P_CBE[7:0]# lines. It is stable and valid one clock after the address phase. For data phases,
P_PAR64 is stable and valid one clock after either P_IRDY# is asserted on a write or
P_TRDY# is asserted on a read.Once P_PAR64 is valid, it remains valid until one clock after
the completion of the current data phase. The master drives P_PAR64 for address and write
data phases; and the target, for read data phases.
P_PERR#
BIDIRECTIONAL - LVTTL with Pull-Up Resistor: Parity Error. This signal is used to report
data parity errors during all PCI-X transactions except a Special Cycle. This signal is
asserted two clock cycles after the error was detected by the device receiving data. The
minimum duration of P_PERR# is one clock for each data phase where an error is detected.
A device cannot report a parity error until it has claimed the access by asserting
P_DEVSEL# and completed a data phase.
P_REQ#
OUTPUT - LVTTL. Request: This signal indicates to the bus arbiter that the GD31244
desires use of the bus. This is a point-to-point signal and every bus master has its own
P_REQ#.
