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SA-1110 Developers Manual 159
Memory and PC-Card Control Module
Figure 10-8. SDRAM 8-Beat Read/Write Timing for 4 Bank x 4 M x 4 Bit Organization (64 Mbit)
A6637-02
CPU Clock
Memory
Clock
SDCLK
SDCKE
command
DRA13-12
DRA11
DRA10
DRA9-0
nCAS/DQM
nSDRAS
nRAS/nSDCS
nSDCAS
nWE (WRIT)
ACT ACT
READ
WRIT
READ
WRIT
READAP
WRITEAP
D (READ)
RD/nWR
(READ)
RD/nWR
(WRIT)
Contents of DRAM register fields:
MDCNFG:DTIM0=1 MDCNFG:DWID0=0 MDCAS00=0101 0101 0101 0101 0101 0101 0101 1111(binary)
MDCNFG:DRAC0=5 MDCNFG:CDB20=0 MDCNFG:TRP0=2 MDCNGF:TDL0=2 MDCNFG:TWR0=3
D (WRIT)
first
last
time
Bank Bank
Row Row
12345678910111213141516171819202122
Trcd
TDL
TRP+1
nWE
(READ)
Row Row
Row
Col
Col Col Col Col Col Col Col Col CRow
Col
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1
D0 D1 D2 D3 D4 D5 D6 D7 D
D
TDL+TRP+2
TRP+TWR+1