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Epson Research and Development
Vancouver Design Center
S1D13505 Hardware Functional Specification
X23A-A-001-14 Issue Date: 01/02/02
Figure 7-45: CRT A.C. Timing
1. t8
min
= [((REG[09h] bits 1:0, REG[08h] bits 7:0)+1) + ((REG[0Ah] bits 6:0)+1)] lines
2. t9
min
= [((REG[0Ch] bits 2:0)+1)] lines
3. t12
min
= [((REG[06h] bits 4:0)+1)*8] Ts
Symbol Parameter Min Typ Max Units
t1
VRTC cycle time
note 1
t2
VRTC pulse width low
note 2
t3
VRTC falling edge to FPLINE falling edge
phase difference
note 3
t3
HRTC
t1
VRTC
t2