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Epson Research and Development
Vancouver Design Center
S1D13505 Hardware Functional Specification
X23A-A-001-14 Issue Date: 01/02/02
60ns
FPM-DRAM
MCLK = 25MHz
• CRT.
• Simultaneous CRT + Single Panel.
• Simultaneous CRT + Dual
Monochrome/Color Panel with Half
Frame Buffer Disabled.
25 4.16 4.16 4.16 3.97 1.11
• Single Panel.
• Dual Monochrome/Color Panel with Half
Frame Buffer Disabled.
25 4.16 4.16 4.16 3.92 0.26
12.5 4.16 4.16 4.16 4.16 4.16
• Dual Monochrome with Half Frame Buffer
Enabled.
25 3.92 3.19 - - -
12.5 4.16 4.16 4.16 4.16 2.46
8.3 4.16 4.16 4.16 4.16 4.16
• Simultaneous CRT + Dual Monochrome
Panel with Half Frame Buffer Enable.
25 3.97 3.40 - - -
• Dual Color Panel with Half Frame Buffer
Enabled.
12.5 4.16 4.16 4.16 3.92 -
8.33 4.16 4.16 4.16 4.16 4.16
Table 14-6: Theoretical Maximum Bandwidth M byte/sec, Cursor/Ink disabled (Continued)
DRAM Type
1
(Speed Grade)
640x480 Display
Max. Pixel
Clock
(MHz)
Maximum Bandwidth (M byte/sec)
1 bpp 2 bpp 4 bpp 8 bpp 16 bpp
