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4.5 BU1923F (IC51) : RDS decoder
•Pin layout
• Block diagram
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
QUAL
RDATA
Vref
MUX
VDD1
VSS1
VSS3
CMP
RCLK
N.C.
XO
XI
VDD2
VSS2
T1
T2
-
+
8th Switched
capacitor filter
PLL
57kHz
RDS/ARI
PLL
1187.5Hz
Bi-phase
decoder
Differential
decoder
Measurement
circuit
Reference
clock
100k
100k
120k
anti-aliasing
filter
comparator
Analog
Power supply
Digital
Power supply
4
3
5
6
12
11
13
14
10 9
7
8
16
1
2
MUX
Vref
VDD1
VSS1
VDD2
VSS2
Xl
X0
T1
T2
RDAT
A
QUAL
RCLK
CMP
VSS3