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SPRZ153
TMS320C6201 Silicon Errata
21
EMIF: HOLD Request Causes Problems With SDRAM Refresh
Advisory 2.1.14
Revision(s) Affected: 2.1 and 2.0
Details: If the HOLD interface is used in a system with SDRAM, there are some situations that are
likely to occur.
If the NOHOLD bit is not set and an external requester attempts to gain control of the bus via
the HOLD signal of the EMIF at the exact same time when the EMIF is issuing a SDRAM
Refresh command, the HOLD request is never recognized. Even if the NOHOLD bit is set in
the EMIF Global Control Register, SDRAM refreshes are still disabled as long as the HOLD
request is pending. A single refresh after receiving the HOLD request is issued, but no
additional refreshes are issued until the HOLD request is removed. The C62xt still owns the
bus since the NOHOLD bit is set.
In addition, if an SDRAM burst is started just prior to a HOLD request, it is possible that the
request will not be recognized until a refresh occurs. This will potentially allow for the HOLD
request to be ignored for several microseconds. (Internal reference number 0757 and 0777)
Workaround: Do not allow a requester to activate the HOLD line without acknowledging it for longer than the
SDRAM refresh period. A workaround can be accomplished by keeping the NOHOLD bit set
and software-polling the HOLD bit of the EMIF Global Control Register. Software-polling of the
HOLD bit in the EMIF Global Control Register will indicate when a HOLD request has been
received (this can be done in the SD_INT service routine or Timer interrupt service routine).
Upon detecting a HOLD request, SDRAM refreshes are disabled, NOHOLD bit is cleared, and
a pulse is generated on the input HOLD signal (can use DMACx as a general-purpose output
pin in combination with the requesters HOLD signal). Then, NOHOLD can be set and SDRAM
refreshes enabled in anticipation of the next HOLD request.
DMA Priority Ignored by PBUS
Advisory 2.1.15
Revision(s) Affected: 2.1 and 2.0
Details: The CPU always has priority over the DMA when accessing peripherals. The DMA PRI bit is
ignored and treated as “0”. (Internal reference number 0540)
Workaround: Leave sufficient gaps in CPU accesses to the PBUS to allow the DMA time to gain adequate
access.