24888 Rev 3.03 - July 12, 2004 AMD-8151
TM
AGP Tunnel Data Sheet
29
Clock Control Register DevA:0xF0
See section 4.3.1 for details on clock gating. AMD system recommendations for System Management Action
Field (SMAF) codes are: 0=ACPI C2; 1=ACPI C3; 2=FID/VID change; 3=ACPI S1; 4=ACPI S3; 5=Throt-
tling; 6=ACPI S4/S5. For server and desktop platforms, AMD recommends setting this register to 0004_0008h
(to gate clocks during S1). For mobile platforms, AMD recommends setting this register to 0004_0A0Ah (to
gate clocks during C3 and S1).
Default: 0000 0000h. Attribute: Read-write.
6:5 ACTL: link side A PHY control value. Read-write. These two bits combine to specify the PHY
compensation value that is applied to side A of the tunnel as follows:
ACTL
Description
00b Apply CALCCOMP directly as the compensation value.
01b Apply ADATA directly as the compensation value.
10b Apply the sum of CALCCOMP and ADATA as the compensation value. In
DevA:0x[E4, E0], if the sum exceeds 13h, then 13h is applied. In DevA:0x[E8], if the
sum exceeds 1Fh, then 1Fh is applied.
11b Apply the difference of CALCCOMP minus ADATA as the compensation value. If the
difference is less than 01h, then 01h is applied.
The default value of this field (from PWROK reset) is controlled by the CMPOVR signal. If
CMPOVR = 0, the default is 00b. If CMPOVR = 1, the default is 01b.
4:0 ADATA: link side A data value. Read-write. This value is applied to the side A of the tunnel PHY
compensation as described in ACTL. The default for DevA:0x[E4, E0] is 08h. The default for
DevA:0xE8 is 0Fh.
Bits Description
31:19 Reserved.
18 CGEN: clock gate enable. 1=Internal clock gating, as specified by bits[7:0] of this register, is
enabled.
17 Must be low. This bit is required to be low at all times; setting it high results in undefined behavior.
16 Must be low. This bit is required to be low at all times; setting it high results in undefined behavior.
15:8 ECGSMAF: external clock gating system management action fields. Each of the bits of this field
correspond to SMAF values that are captured in Stop Grant cycles from the host. For each bit,
1=When LDTSTOP# is asserted prior to a Stop Grant cycle in which the SMAF field matches the
ECGSMAF bit that is asserted, then A_PCLK and internal clock grids associated with the AGP
bridges are forced low. 0=A_PCLK and the internal clock grids are active while LDTSTOP# is
asserted. For example, if A_PCLK gating is required for SMAF values of 3 and 5, then ECGSMAF[3,
5] must be high. See section 4.3.1 for details.
7:0 ICGSMAF: internal clock gating system management action fields. Each of the bits of this field
correspond to SMAF values that are captured in Stop Grant cycles from the host. For each bit,
1=When LDTSTOP# is asserted prior to a Stop Grant cycle in which the SMAF field matches the
ICGSMAF bit that is asserted, then the IC power is reduced through gating of internal clocks. 0=No
power reduction while LDTSTOP# is asserted. For example, if clock gating is required for SMAF
values of 3 and 5, then ICGSMAF[3, 5] must be high. See section 4.3.1 for details.
