24888 Rev 3.03 - July 12, 2004 AMD-8151
TM
AGP Tunnel Data Sheet
33
DevB:0x24. Default: 0000 FFF0h Attribute: Read-write.
DevB:0x30. Default: 0000 FFFFh Attribute: Read-write.
AGP Bridge Interrupt and Bridge Control Register DevB:0x3C
Default: 0000 00FFh Attribute: See below.
Bits Description
31:20 PMEMLIM. Prefetchable memory limit address bits[31:20]. See DevB:0x[30:1C] above.
19:16 Reserved.
15:4 PMEMBASE. Prefetchable memory base address bits[31:20]. See DevB:0x[30:1C] above.
3:0 Reserved.
Bits Description
31:16 IOLIM. IO limit address bits[31:16]. See DevB:0x[30:1C] above.
15:0 IOBASE. IO base address bits[31:16]. See DevB:0x[30:1C] above.
Bits Description
31:23 Reserved.
22 SBRST: AGP bus reset. Read-write. 1=A_RESET# asserted; AGP bus placed into reset state.
0=A_RESET# not asserted.
21:20 Reserved.
19 VGAEN: VGA decoding enable. Read-write. 1=Host-initiated commands targeting VGA-
compatible address ranges are routed to the AGP bus. These include memory accesses from A0000h
to BFFFFh (within the bottom megabyte of memory space only), IO accesses in which address
bits[9:0] range from 3B0h to 3BBh or 3C0h to 3DFh (address bits[15:10] are not decoded, regardless
of DevB:0x3C[ISAEN]; also this only applies to the first 64K of IO space; i.e., address bits[31:16]
must be low). 0=The IC does not decode VGA-compatible address ranges.
18 ISAEN: ISA decoding enable. Read-write. 1=The IO address window specified by
DevB:0x1C[15:0] and DevB:0x30 is limited to the first 256 bytes of each 1K byte block specified;
this only applies to the first 64K bytes of IO space. 0=The PCI IO window is the whole range
specified by DevB:0x1C[15:0] and DevB:0x30.
17:16 Reserved.
15:8 INTERRUPT_PIN. Read; write once. These bits control no internal logic.
7:0 INTERRUPT_LINE. Read-write. These bits control no internal logic.
