24888 Rev 3.03 - July 12, 2004 AMD-8151
TM
AGP Tunnel Data Sheet
7
3.2 Tunnel Link Signals
The following are signals associated with the HyperTransport
TM
links. [B, A] in the signal names below refer
to the A and B sides of the tunnel. [P, N] are the positive and negative sides of differential pairs.
* The signals connected to the A side of the tunnel are powered by VDD12A and the signals connected to the
B side of the tunnel are powered by VDD12B.
** Diff High and Diff Low for these link pins specifies differential high and low; e.g., Diff High specifies that
the _P signal is high and the _N signal is low.
If one of the sides of the tunnel is not used on a platform then the unconnected link should be treated as fol-
lows, for every 10 differential pairs: connect all of the _P differential inputs together and through a resistor to
VSS; connect all the _N differential inputs together and through a resistor to VDD12; leave the differential out-
puts unconnected. If there are unused link signals on an active link (because the IC is connected to a device
with a reduced bit width), then the unused differential inputs and outputs should also be connected in this way.
Pin name and description IO cell
type
Power
plane*
During
reset
After
reset
LDTCOMP[3:0].
Link compensation pins for both sides of the tunnel. These are
designed to be connected through resistors as follows:
Bit
Function External Connection
[0] Positive receive compensation Resistor to VDD12B
[1] Negative receive compensationResistor to VSS
[3, 2] Transmit compensation Resistor from bit [2] to bit [3]
These resistors are used by the compensation circuit. The output of this circuit is
combined with DevA:0x[E8, E4, E0] to determine compensation values that are
passed to the link PHYs.
Analog VDD-
12B
LRACAD_[P, N][15:0]; LRBCAD_[P, N][7:0]. Receive link command-address-
data bus.
Link
input
VDD12
LRACLK[1, 0]_[P, N]; LRBCLK0_[P, N]. Receive link clock. Link
input
VDD12
LR[B, A]CTL_[P, N]. Receive link control signal. Link
input
VDD12
LTACAD_[P, N][15:0]; LTBCAD_[P, N][7:0]. Transmit link command-address-
data bus.
Link
output
VDD12 Diff
High**
Func.
LTACLK[1, 0]_[P, N]; LTBCLK0_[P, N]. Transmit link clock. Link
output
VDD12 Func. Func.
LT[B, A]CTL_[P, N]. Transmit link control signal. Link
output
VDD12 Diff
Low**
Func.
