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SiI 141B SiI-DS-0037-C
Silicon Image, Inc. 5 Subject to Change without Notice
Timing Diagrams
Figure 1. Digital Output Transition Times
R
CIH
R
CIL
R
CIP
2.0 V
0.8 V
0.8 V
2.0 V 2.0 V
Figure 2. Receiver Clock Cycle/High/Low Times
Figure 3. Channel-to-Channel Skew Timing
Output Timing
Figure 4. Output Data Setup/Hold Times to ODCK
10pF (5pF)SiI141B
D
LHT
D
HLT
2.0 V 2.0 V
0.8 V 0.8 V
ODCK_INV = 0
QE[23:0]/QO[23:0],
DE, VSYNC, HSYNC,
CTL[3:1]
T
SETUP
ODCK_INV = 1
T
HOLD
RX1
RX2
V
DIFF
= 0V
RX0
V
DIFF
= 0VT
CCS