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TMS320C25, TMS320E25
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
31
RS, INT, BIO, AND XF TIMING
switching characteristics over recommended operating conditions (see Note 3 and 8)
PARAMETER MIN TYP MAX UNIT
t
d(RS)
CLKOUT1 low to reset state entered 22
†
ns
t
d(IACK)
CLKOUT1 to IACK valid – 6 0 12 ns
t
d(XF)
XF valid before falling edge of STRB Q – 15 ns
NOTES: 3. Q = 1/4t
c(C)
.
8. RS
, INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is
met, the exact sequence shown in the timing diagrams will occur.
timing requirements over recommended operating conditions (see Note 3 and 8)
MIN NOM MAX UNIT
t
su(IN)
INT/BIO/RS setup before CLKOUT1 high 32 ns
t
h(IN)
INT/BIO/RS hold after CLKOUT1 high 0 ns
t
f(IN)
INT/BIO fall time 8
†
ns
t
w(IN)
INT/BIO low pulse duration t
c(C)
ns
t
w(RS)
RS low pulse duration 3
tc(C)
ns
†
Value derived from characterization data and not tested.
NOTES: 3. Q = 1/4t
c(C)
.
8. RS
, INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is
met, the exact sequence shown in the timing diagrams will occur.
HOLD TIMING
switching characteristics over recommended operating conditions (see Note 3)
PARAMETER MIN TYP MAX UNIT
t
d(C1L-AL)
HOLDA low after CLKOUT1 low 0 10 ns
t
dis(AL-A)
HOLDA low to address three-state 0
†
ns
t
dis(C1L-A)
Address three-state after CLKOUT1 low (HOLD mode, see Note 9) 20
†
ns
t
d(HH-AH)
HOLD high to HOLDA high 25 ns
t
en(A-C1L)
Address driven before CLKOUT1 low (HOLD mode, see Note 9) 8
†
ns
†
Value derived from characterization data and not tested.
NOTES: 3. Q = 1/4t
c(C)
.
9. A15-A0, PS, DS, IS, STRB, and R/W timings are all included in timings referenced as “address.”
timing requirements over recommended operating conditions (see Note 3)
MIN NOM MAX UNIT
t
d(C2H-H)
HOLD valid after CLKOUT2 high Q – 24 ns
NOTE 3: Q = 1/4t
c(C)
.
ADVANCE INFORMATION