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excellent high
frequency
characteristics
compara-
ble
lo those
of a small-signal
transistor.
Further-
more, becanse
lhere is
no time clonstant
in the
NFB
circuit
ir-r
the lorv-frecluency
region,
amplification
is
possibie
dorvn
to
DC
(DC
inputs
will be
cut off,
hor,vever,
by the input
coupling
capacitor).
'I'he
circuit
features
described
above
provide
an
extremely wide
polver
frequency
range
(60W
+
60W, 101-lz
to ZOkHz, THD
0.005Va,
Bdl).
High
Speed
Bias
Servocontrol Circuit
By
operating the
power
stage
only within
the
active region
(no
possible
cut-off)
and with mini-
mr-rm
idle current,
the high speed
bias servocontrol
circuit
prevents
the
generation
of switching
dis-
tortion and
reduces heaf loss.
Operating Principle
Since
idle current flows
through
normal class
B
SI)PP
porver
stages
(see
Fig.
4-10)
when
no signal
is
appliecl,
the
DC level
is shifted by D
and VR
by
a fixed
amount
(w'itir
the
voltage
across
points
X
ancl
Y
sen'ing as a bias). The voltages
across
points
X
and
Z,
and
Z
and
Y
at this
time will be equal.
When
the
positve
portion
of a signal is applied to
this
circuit,
the
porver
stage current
on
the
NPN
side is increased,
and the
voltage (Vn1)
across both
ends
of
RB1
also heing
increased,
resulting in
the
voitage
across
point
X and
Z
being
increased.
However,
since
the
voltage across
points
X and
Y
is
practically
constant, the voltage
across
points
Z
anrl
Y
(PNP power
stage bias) will
be decreased,
resulting in
the
PNP
power
stage
being
cut
off.
'I'he
high
speed bias
servocontrol
circuit in-
creases
the
voltage
across
points
X
and
Y
by the
same
amount
as the
voltage
increase
across
points
X and
Z,
thereby cancelling
the voltage
decrease
across
poinls
Z
and
Y,
and
preventing
the
PNP
polver
stage from being
cut off.
This
high speed
bias servocontrol
circuit
is out-
lined
in
Fig.
4-11. lVhen
there is no
signal applied
to the
crrcuit,
Q1
and
Q2
are almost
cut off,
while
Q3
and
Q4
u'ill
be on.
The
voitage
across
fhe
collector
and
base
of both
of these
transistors
(Q3
and
Q4)
at this time may
be disregarded. Con-
sequently,
rvith
the
power
stage bias circuit con-
sisting of
,tr
PN
junctions
formed
by
Q3,
D3,
and
Q4,
and
VR1.
this circuit
is equivalent
to the
previous
circuil
shown in
Fig.
4-10.
With
R1
and
D1
ensuring
a constant
flow of cur-
rent, the base
of
Q1
and
point
Z
may be
brought
to
the
same level
on an AC
basis
(level
fluctuations
due to the
signal) by
a simple shift in DC
level.
Furthermore,
Qf
may
be considered
emitter-
follower
lvitli R3
as the
emitter resistance.
sx-3aclo
When
the voltage
across
points
X and
Z
is
in-
creased
by tl're
positive portion
of the signal
ap-
plied
to
this circuit,
it becomes
the input
signal
of this emitter-follower
(Q1).
Since
the emitter-
follower voltage
gain
is
practically
1-,
a
voltage
more or less equal to that
of
the input
signal
(that
is,
the voltage increase across
points
X and Z)
is
produced
at
R3.
And
the R3 voltage is
the voltage
applied
across the base and collector
of
QB
which
forms
part
of the
power
stage
bias circuit. So
the
bias voltage
applied to
Q3
will be in
excess by
the
same amount
that the voltage across
points
X
and
Z
is increased
(by positive portion
of
the signal)
above
the
voltage
level
when no signal
is being
applied.
Consequently,
the increase
in
voltage
across
points
X
and
Z cancels
the decrease
in
volt-
age
across
points
Z
and
Y,
thereby
maintaining
the idle current
without
cutting the
PNP
power
stage
off
(noting
that there
actually
is a slight
decrease
in current).
For
the negative
portions
of
the signal,
Q3
and
Q4
are operated
in
the same
rnanner,
thereby
preventing
the
NPN
power
stage
from
being cut
off.
In
other words,
the high speed
bias servocontrol
circuit
acts to
prevent
any
"poler
stage cut-off"
signals
from
being
applied to the
polyer
stage.
Fig. 4-'l
0
Normal
power
stage bias circuit
PRE-
ORIVER
PFE.
ORIVER
Fig.
4-1 1
High
speed bias servocontrol
circuit
IJ