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1.4 System-level Block Diagram
Figure 2. Typical Stand-alone Configuration
DVDDA
Panel Interface
SVDDA
SGNDA
OSC
ADC
RVDDA
Host Interface
DGNDA
Clock Generator
ADC_VDD
gmZAN1 Core
ADC_GND
ADC
RGNDA
TCLK
R1
R
R1
R
RVDDA
R1
R
R1
R
R1
R
Video Connector
C1
C
L2
Vsync
C2
C
L1
Hsync
CVDD
Red
Blue
Green
On-Screen
Display
Controller
MPU with
EPROM
R+,G+,B+
OSD-FSW OSD-FSW
OSD-CLK
OSD-HREF
OSD-VREF
4
IRQ
HES
HCLK
HDATA
12
MFBs
RESETn
CVSS
TFT Panel
24
Even Data
PCLKA
PHS
PVS
PDISPE
Odd Data
24
Power
Switching
Module
Pbias
Power
Switching
Module
Pbias
+12V
+5/3.3V
To Clock
Generator