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11. SCHEMATIC DIAGRAM
I). TOP-LEVEL FLOW
PAGE 4
POWER
+12V
+5V
+3.3V
PAGE 3
ZAN1
TCLK1
+3.3V
+5V
+12V
MFB2
MFB7
MFB8
MFB9
/VGA_CON
RXD
TXD
HCLK
HFS
IRQ
HDATA0
RST
SDA
SCL
RST1
MFB1
MFB2
PDISPE
PVS
PHS
PCLK
OBLU
OGRN
ORED
EBLU
EGRN
ERED
PAGE 6
LVDS
ERED
EGRN
EBLU
OBLU
OGRN
ORED
PCLK
PHS
PVS
PDISPE
763-17.DSN
A
TOP LEVEL
AOC (Top Victory) Electronics Co., Ltd.
A
26
Monday, December 11, 2000
Title
Size Document Number Rev
Date: Sheet of
PAGE 2
MICRO CONTROLLER
/VGA_CON
HDATA0
MFB7
MFB8
MFB9
HCLK
HFS
RXD
TXD
IRQ
MFB2
SDA
SCL
+5V
TCLK1
RST
RST1
MFB1
MFB2
.Gmzan1 bloc
k
MCU
LVDS bloc
k
P
owe
r
b
l
ock