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1.5 Operating Modes
The Source Clock (also called SCLK in this document) and the Panel Clock are defined as follows:
z The Source Clock is the sample clock regenerated from the input Hsync timing (called clock recovery) by
SCLK DDS (direct digital synthesis) and the PLL.
z The Panel Clock is the timing clock for panel data at the single pixel per clock rate. The actual PCLK to the
panel may be one-half of this frequency for double-pixel panel data format. When its frequency is different from
that of source clock, the panel clock is generated by Destination Clock (or DCLK) DDS/PLL.
There are six display modes: Native, Slow DCLK, Zoom, Downscaling, Destination Stand Alone, and Source Stand
Alone.
Each mode is unique in terms of:
z Input video resolution vs. panel resolution
z Source Clock frequency / Panel Clock frequency ratio
z Source Hsync frequency / Panel Hsync frequenc ratio
z Data source (analog RGB, panel background color, on-chip pattern generator
1.5.1 Native
Panel Clock frequency = Source Clock frequency
Panel Hsync frequency = Input Hsync frequency
Panel Vsync frequency = Input Vsync frequency
This mode is used when the input resolution is the same as the panel resolution and the input data clock frequency is
within the panel clock frequency specification of the panel being used.
1.5.2 Slow DCLK
Panel Clock frequency < Source Clock frequency
Panel Hsync frequency = Input Hsync frequency
Panel Vsync frequency = Input Vsync frequency
This mode is used when the input resolution is the same as the panel resolution, but the input data clock frequency is
exceeds the panel clock frequency specification of the panel being used. The panel clock is scaled to the Source Clock,
and the internal data buffers are used to spread out the timing of the input data by making use of the large CRT
blanking time to extends the panel horizontal display time.
1.5.3 Zoom
Panel Clock frequency > Source Clock frequency
Panel Hsync frequency > Input Hsync frequency
Panel Vsync frequency = Input Vsync frequency
This mode is used when the input resolution is less than the panel resolution. The input data clock is then locked to the
pnael clock, which is at a higher frequency. The input data is zoomed to the panel resolution.