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1.4.4.1 Clock Generator Control Register 1 (CGCR1) [1C20h]
The clock generator control register 1 (CGCR1) is shown in Figure 1-6 and described in Table 1-13.
Figure 1-6. Clock Generator Control Register 1 (CGCR1) [1C20h]
15 14 13 12 11 8
Reserved Reserved PLL_PWRDN M
R/W-0 R/W-0 R/W-1 R/W-0
7 6 5 4 3 2 1 0
M
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-13. Clock Generator Control Register 1 (CGCR1) Field Descriptions
Bit Field Value Description
15 Reserved 0 This bit must be set to 1 for normal operation.
14-13 Reserved 0 Reserved. This bit must be always written to be zero.
12 PLL_PWRDN PLL power down bit. This bit is used to power down the PLL when it is not being used.
0 PLL is powered up.
1 PLL is powered down.
11-0 M 0-FFFh PLL multiplier value bits. These bits define the PLL multiplier value. Multiplier value = M + 4.
1.4.4.2 Clock Generator Control Register 2 (CGCR2) [1C21h]
The clock generator control register 2 (CGCR2) is shown in Figure 1-7 and described in Table 1-14.
Figure 1-7. Clock Generator Control Register 2 (CGCR2) [1C21h]
15 14 12 11 0
RDBYPASS Reserved RDRATIO
R/W-0 R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-14. Clock Generator Control Register 2 (CGCR2) Field Descriptions
Bit Field Value Description
15 RDBYPASS Reference divider bypass control. When this bit is set to 1 the PLL reference divider is bypassed
(i.e., F
PLLIN
= F
CLKREF
). When this bit is set to 0, the reference clock to the PLL is divided by the
reference divider (i.e., F
PLLIN
= F
CLKIN
/ (RDRATIO+4)). The RDRATIO bits specify the divider value.
0 Use the reference divider.
1 Bypass the reference divider.
14-12 Reserved 0 Reserved.
11-0 RDRATIO 0-FFFh Divider ratio bits for the reference divider. Divider value = RDRATIO + 4. For example, setting
RDRATIO = 0 means divide the input clock rate by 4.
30
System Control SPRUFX5A–October 2010–Revised November 2010
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