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System Configuration and Control
1.7.7 EMIF Clock Divider Register (ECDR) [1C26h]
The EMIF clock divider register (ECDR) controls the input clock frequency to the EMIF module. When
EDIV = 1 (default), the EMIF operates at the same clock rate as the system clock (SYSCLK). When EDIV
= 0, the EMIF operates at half the clock rate of the system clock.
This register affects both asynchronous memory mode timing as well as synchronous (mobile SDRAM,
SDRAM) mode. But half-rate mode is normally only needed to meet synchronous memory timing. For
more information regarding when half-rate mode is required, see the mSDRAM timing sections of the
device-specific data sheet.
The EMIF clock divider register (ECDR) is shown in Figure 1-49 and described in Table 1-63.
Figure 1-49. EMIF Clock Divider Register (ECDR) [1C26h]
15 1 0
Reserved EDIV
R-0 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-63. EMIF Clock Divider Register (ECDR) Field Descriptions
Bit Field Value Description
15-1 Reserved 0 Reserved.
0 EDIV EMIF clock divider select bits. The EMIF module can internally divide its input peripheral clock.
When this bit is set to 0, the EMIF operates at half the clock rate of its peripheral clock. When this
bit is set to 1 the EMIF operates at the full rate of its peripheral clock.
0 EMIF operates at half the peripheral clock rate.
1 EMIF operates at the same rate as the peripheral clock.
77
SPRUFX5A–October 2010–Revised November 2010 System Control
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