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Preface
SPRUFX5A–October 2010–Revised November 2010
Read This First
About This Manual
This document describes various aspects of the TMS320C5515 digital signal processor (DSP) including:
system memory, device clocking options and operation of the DSP clock generator, power management
features, interrupts, and system control.
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
The following documents describe the TMS320C5515/14/05/04 Digital Signal Processor (DSP) Digital
Signal Processor (DSP). Copies of these documents are available on the internet at http://www.ti.com.
SWPU073 — TMS320C55x 3.0 CPU Reference Guide. This manual describes the architecture,
registers, and operation of the fixed-point TMS320C55x digital signal processor (DSP) CPU.
SPRU652 — TMS320C55x DSP CPU Programmer’s Reference Supplement. This document describes
functional exceptions to the CPU behavior.
SPRUFO1A — TMS320C5515/14/05/04/VC05/VC04 Digital Signal Processor (DSP) Inter-Integrated
Circuit (I2C) Peripheral User's Guide. This document describes the inter-integrated circuit (I2C)
peripheral in the TMS320C5515/14/05/04/VC05/VC04 Digital Signal Processor (DSP) devices. The
I2C peripheral provides an interface between the device and other devices compliant with Phillips
Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an
I2C-bus. This document assumes the reader is familiar with the I2C-bus specification.
SPRUFO2 — TMS320C5515/14/05/04/VC05/VC04 Digital Signal Processor (DSP) Timer/Watchdog
Timer User's Guide. This document provides an overview of the three 32-bit timers in the
TMS320C5515/14/05/04/VC05/VC04 Digital Signal Processor (DSP) devices. The 32-bit timers of
the device are software programmable timers that can be configured as general-purpose (GP)
timers. Timer 2 can be configured as a GP, a Watchdog (WD), or both simultaneously.
SPRUFO3 — TMS320C5515/14/05/04/VC05/VC04 Digital Signal Processor (DSP) Serial Peripheral
Interface (SPI) User's Guide. This document describes the serial peripheral interface (SPI) in the
TMS320C5515/14/05/04/VC05/VC04 Digital Signal Processor (DSP) devices. The SPI is a
high-speed synchronous serial input/output port that allows a serial bit stream of programmed
length (1 to 32 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The
SPI supports multi-chip operation of up to four SPI slave devices. The SPI can operate as a master
device only.
9
SPRUFX5A–October 2010–Revised November 2010 Read This First
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