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List of Figures
1-1. Functional Block Diagram ................................................................................................ 13
1-2. DSP Memory Map ........................................................................................................ 17
1-3. DSP Clocking Diagram .................................................................................................. 22
1-4. Clock Generator ........................................................................................................... 24
1-5. CLKOUT Control Source Select Register (CCSSR) [1C24h]........................................................ 25
1-6. Clock Generator Control Register 1 (CGCR1) [1C20h] .............................................................. 30
1-7. Clock Generator Control Register 2 (CGCR2) [1C21h] .............................................................. 30
1-8. Clock Generator Control Register 3 (CGCR3) [1C22h] .............................................................. 31
1-9. Clock Generator Control Register 4 (CGCR4) [1C23h] .............................................................. 31
1-10. Clock Configuration Register 1 (CCR1) [1C1Eh]...................................................................... 32
1-11. Clock Configuration Register 2 (CCR2) [1C1Fh]...................................................................... 32
1-12. Idle Configuration Register (ICR) [0001h].............................................................................. 36
1-13. Idle Status Register (ISTR) [0002h]..................................................................................... 37
1-14. Peripheral Clock Gating Configuration Register 1 (PCGCR1) [1C02h] ............................................ 39
1-15. Peripheral Clock Gating Configuration Register 2 (PCGCR2) [1C03h] ............................................ 41
1-16. Peripheral Clock Stop Request/Acknowledge Register (CLKSTOP) [1C3Ah] .................................... 42
1-17. USB System Control Register (USBSCR) [1C32h] ................................................................... 44
1-18. RTC Power Management Register (RTCPMGT) [1930h]............................................................ 46
1-19. RTC Interrupt Flag Register (RTCINTFL) [1920h] .................................................................... 47
1-20. RAM Sleep Mode Control Register1 [0x1C28] ........................................................................ 48
1-21. RAM Sleep Mode Control Register2 [0x1C2A] ........................................................................ 49
1-22. RAM Sleep Mode Control Register3 [0x1C2B] ........................................................................ 49
1-23. RAM Sleep Mode Control Register4 [0x1C2C]........................................................................ 49
1-24. RAM Sleep Mode Control Register5 [0x1C2D]........................................................................ 49
1-25. IFR0 and IER0 Bit Locations............................................................................................. 54
1-26. IFR1 and IER1 Bit Locations............................................................................................. 55
1-27. Die ID Register 0 (DIEIDR0) [1C40h]................................................................................... 58
1-28. Die ID Register 1 (DIEIDR1) [1C41h]................................................................................... 58
1-29. Die ID Register 2 (DIEIDR2) [1C42h]................................................................................... 58
1-30. Die ID Register 3 (DIEIDR3[15:0]) [1C43h] ............................................................................ 59
1-31. Die ID Register 4 (DIEIDR4) [1C44h]................................................................................... 59
1-32. Die ID Register 5 (DIEIDR5) [1C45h]................................................................................... 59
1-33. Die ID Register 6 (DIEIDR6) [1C46h]................................................................................... 60
1-34. Die ID Register 7 (DIEIDR7) [1C47h]................................................................................... 60
1-35. External Bus Selection Register (EBSR) [1C00h]..................................................................... 61
1-36. RTC Power Management Register (RTCPMGT) [1930h]............................................................ 63
1-37. LDO Control Register (LDOCNTL) [7004h] ............................................................................ 65
1-38. Output Slew Rate Control Register (OSRCR) [1C16h]............................................................... 66
1-39. Pull-Down Inhibit Register 1 (PDINHIBR1) [1C17h] .................................................................. 67
1-40. Pull-Down Inhibit Register 2 (PDINHIBR2) [1C18h] .................................................................. 68
1-41. Pull-Down Inhibit Register 3 (PDINHIBR3) [1C19h] .................................................................. 69
1-42. DMA Interrupt Flag Register (DMAIFR) [1C30h] ...................................................................... 72
1-43. DMA Interrupt Enable Register (DMAIER) [1C31h]................................................................... 72
1-44. DMAn Channel Event Source Register 1 (DMAnCESR1) [1C1Ah, 1C1Ch, 1C36h, and 1C38h] .............. 73
1-45. DMAn Channel Event Source Register 2 (DMAnCESR2) [1C1Bh, 1C1Dh, 1C37h, and 1C39h] .............. 73
1-46. Peripheral Software Reset Counter Register (PSRCR) [1C04h].................................................... 74
1-47. Peripheral Reset Control Register (PRCR) [1C05h] .................................................................. 74
4
List of Figures SPRUFX5A–October 2010–Revised November 2010
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