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1-48. Output Slew Rate Control Register (OSRCR) Field Descriptions................................................... 66
1-49. Pull-Down Inhibit Register 1 (PDINHIBR1) Field Descriptions ...................................................... 67
1-50. Pull-Down Inhibit Register 2 (PDINHIBR2) Field Descriptions ...................................................... 68
1-51. Pull-Down Inhibit Register 3 (PDINHIBR3) Field Descriptions ...................................................... 69
1-52. Channel Synchronization Events for DMA Controllers ............................................................... 71
1-53. System Registers Related to the DMA Controllers ................................................................... 71
1-54. DMA Interrupt Flag Register (DMAIFR) Field Descriptions.......................................................... 72
1-55. DMA Interrupt Enable Register (DMAIER) Field Descriptions....................................................... 72
1-56. DMAn Channel Event Source Register 1 (DMAnCESR1) Field Descriptions ..................................... 73
1-57. DMAn Channel Event Source Register 2 (DMAnCESR2) Field Descriptions ..................................... 73
1-58. Peripheral Software Reset Counter Register (PSRCR) Field Descriptions........................................ 74
1-59. Peripheral Reset Control Register (PRCR) Field Descriptions...................................................... 74
1-60. Effect of BYTEMODE Bits on EMIF Accesses ........................................................................ 76
1-61. Effect of USBSCR BYTEMODE Bits on USB Access ................................................................ 76
1-62. EMIF System Control Register (ESCR) Field Descriptions.......................................................... 76
1-63. EMIF Clock Divider Register (ECDR) Field Descriptions ............................................................ 77
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SPRUFX5A–October 2010–Revised November 2010 List of Tables
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