Filter
Top Products
www.ti.com
System Configuration and Control
Table 1-50. Pull-Down Inhibit Register 2 (PDINHIBR2) Field Descriptions (continued)
Bit Field Value Description
5 A20PD EMIF A[20] pin pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down.
0 Pin pull-down is enabled.
1 Pin pull-down is disabled.
4 A19PD EMIF A[19] pin pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down.
0 Pin pull-down is enabled.
1 Pin pull-down is disabled.
3 A18PD EMIF A[18] pin pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down.
0 Pin pull-down is enabled.
1 Pin pull-down is disabled.
2 A17PD EMIF A[17] pin pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down.
0 Pin pull-down is enabled.
1 Pin pull-down is disabled.
1 A16PD EMIF A[16] pin pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down.
0 Pin pull-down is enabled.
1 Pin pull-down is disabled.
0 A15PD EMIF A[15] pin pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down.
0 Pin pull-down is enabled.
1 Pin pull-down is disabled.
The pull-down inhibit register 3 (PDINHIBR3) is shown in Figure 1-41 and described in Table 1-51.
Figure 1-41. Pull-Down Inhibit Register 3 (PDINHIBR3) [1C19h]
15 14 13 12 11 10 9 8
PD15PD PD14PD PD13PD PD12PD PD11PD PD10PD PD9PD PD8PD
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
7 6 5 4 3 2 1 0
PD7PD PD6PD PD5PD PD4PD PD3PD PD2PD Reserved
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-51. Pull-Down Inhibit Register 3 (PDINHIBR3) Field Descriptions
Bit Field Value Description
15 PD15PD Parallel port pin 15 pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down.
0 Pin pull-down is enabled.
1 Pin pull-down is disabled.
14 PD14PD Parallel port pin 14 pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down.
0 Pin pull-down is enabled.
1 Pin pull-down is disabled.
13 PD13PD Parallel port pin 13 pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down.
0 Pin pull-down is enabled.
1 Pin pull-down is disabled.
12 PD12PD Parallel port pin 12 pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down.
0 Pin pull-down is enabled.
1 Pin pull-down is disabled.
11 PD11PD Parallel port pin 11 pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down.
0 Pin pull-down is enabled.
1 Pin pull-down is disabled.
69
SPRUFX5A–October 2010–Revised November 2010 System Control
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated