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STATus
The STATus subsystem controls the SCPI-defined Operation and Questionable
Signal status registers. Each is comprised of a condition register, an event register,
an enable mask, and negative and positive transition filters.
Each status register works as follows: when a condition occurs, the appropriate bit in
the condition register is set or cleared. If the the corresponding transition filter is
enabled for that bit, the same bit is set in the associated event register. The contents
of the event register and the enable mask are logically ANDed bit-for-bit; if any bit
of the result is set, the summary bit for that register is set in the status byte. The
status byte summary bit for the Operation status register is bit 7; for the
Questionable Signal status register, bit 3.
Operation
Status Register All bits are always 0. This register is implemented only for SCPI compatibility
purposes.
Questionable
Signal
Status Register All bits are always 0. This register is implemented only for SCPI compatibility
purposes.
Subsystem Syntax STATus
:OPERation|QUEStionable
:CONDition? [query only]
:ENABle <unmask>
[:EVENt]? [query only]
:NTRansition <unmask>
:PTRansition <unmask>
:PRESet [no query]
:OPERation|QUEStionable:CONDition?
STATus:OPERation|QUEStionable:CONDition? returns the contents of the
appropriate condition register. Reading the register does not affect its contents.
Comments
• Executable when initiated: Yes
• Coupling group: none
• Related commands: STATus subsystem, *SRE, *STB?
• *RST Condition: all bits of both condition registers are cleared as a result of the
state present after *RST.
Example Querying the Operation condition register
STAT:OPER? Query Operation condition register
3-18 E1446/E1405/06 Command Reference STATus Subsystem