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ESAI Programming Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
8-20 Freescale Semiconductor
Figure 8-7 Frame Length Selection
DATA DATA
SERIAL CLOCK
RX, TX FRAME SYNC
WORD LENGTH: TFSL=0, RFSL=0
RX, TX SERIAL DATA
NOTE: Frame sync occurs while data is valid.
DATA DATA
SERIAL CLOCK
RX, TX FRAME SYNC
ONE BIT LENGTH: TFSL=1, RFSL=1
RX, TX SERIAL DATA
NOTE: Frame sync occurs for one bit time preceding the data.
DATA DATA
SERIAL CLOCK
TX FRAME SYNC
MIXED FRAME LENGTH: TFSL=1, RFSL=0
TX SERIAL DATA
RX FRAME SYNC
DATA DATA
RX SERIAL DATA
DATA DATA
SERIAL CLOCK
TX FRAME SYNC
MIXED FRAME LENGTH: TFSL=0, RFSL=1
TX SERIAL DATA
RX FRAME SYNC
DATA DATA
RX SERIAL DATA