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DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
B-12 Freescale Semiconductor
M_PEN EQU 18 ; PLL Enable Bit
M_COD EQU 19 ; PLL Clock Output Disable Bit
M_PD EQU $F00000 ; PreDivider Factor Bits Mask (PD0-PD3)
M_PD0 EQU 20 ;PreDivider Factor bit 0
M_PD1 EQU 21 ;PreDivider Factor bit 1
M_PD2 EQU 22 ;PreDivider Factor bit 2
M_PD3 EQU 23 ;PreDivider Factor bit 3
;------------------------------------------------------------------------
;
; EQUATES for BIU
;
;------------------------------------------------------------------------
; Register Addresses Of BIU
M_BCR EQU $FFFFFB ; Bus Control Register
M_DCR EQU $FFFFFA ; DRAM Control Register
M_AAR0 EQU $FFFFF9 ; Address Attribute Register 0
M_AAR1 EQU $FFFFF8 ; Address Attribute Register 1
M_AAR2 EQU $FFFFF7 ; Address Attribute Register 2
M_AAR3 EQU $FFFFF6 ; Address Attribute Register 3
M_IDR EQU $FFFFF5 ; ID Register
; Bus Control Register
M_BA0W EQU $1F ; Area 0 Wait Control Mask (BA0W0-BA0W4)
M_BA0W0 EQU 0 ;Area 0 Wait Control Bit 0
M_BA0W1 EQU 1 ;Area 0 Wait Control Bit 1
M_BA0W2 EQU 2 ;Area 0 Wait Control Bit 2
M_BA0W3 EQU 3 ;Area 0 Wait Control Bit 3
M_BA0W4 EQU 4 ;Area 0 Wait Control Bit 4