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DAX Internal Architecture
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
10-4 Freescale Semiconductor
10.5 DAX Internal Architecture
Hardware components shown in Figure 10-1 are described in the following sections. The DAX
programming model is illustrated in Figure 10-2.
Figure 10-2 DAX Programming Model
Table 10-1 DAX Interrupt Vectors
Condition Address Description
XAUR VBA:$28 DAX transmit underrun error
XADE & XBLK VBA:$2A DAX block transferred
XADE VBA:$2E DAX audio data register empty
Table 10-2 DAX Interrupt Priority
Priority Interrupt
highest DAX transmit underrun error
DAX block transferred
lowest DAX audio data register empty
23 122122 8
XBLK
347918 17 161920
XADE
06 513 12 11 101415
Reserved bit
0
23
122122 8 36 579
XVA
10
XCB
15
XUB
14
XVB
13
XCA
12
XUA
1118 17 161920 4
0
23
XAUR
XADRA - Audio Data Register A - X:$FFFFD2 and XADRB - Audio Data Register B -X:$FFFFD3
XNADR - Non-Audio Data Register - X:$FFFFD1
XSTR - Status Register - X:$FFFFD4
0
23
122122 8
XCS0
36 5791015 14 13 12 1118 17 161920
XCS1
4
XUIE
XSB
XBIE XDIE
XCTR - Control Register - X:$FFFFD0