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DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
B-18 Freescale Semiconductor
M_XBLK EQU 2 ; DAX Block Transferred (XBLK)
; non-audio bits in XNADR
M_XVA EQU 10 ; DAX Channel A Validity (XVA)
M_XUA EQU 11 ; DAX Channel A User Data (XUA)
M_XCA EQU 12 ; DAX Channel A Channel Status (XCA)
M_XVB EQU 13 ; DAX Channel B Validity (XVB)
M_XUB EQU 14 ; DAX Channel B User Data (XUB)
M_XCB EQU 15 ; DAX Channel B Channel Status (XCB)
; control bits in XCTR
M_XDIE EQU 0 ; DAX Audio Data Register Empty Interrupt Enable (XDIE)
M_XUIE EQU 1 ; DAX Underrun Error Interrupt Enable (XUIE)
M_XBIE EQU 2 ; DAX Block Transferred Interrupt Enable (XBIE)
M_XCS0 EQU 3 ; DAX Clock Input Select 0 (XCS0)
M_XCS1 EQU 4 ; DAX Clock Input Select 1 (XCS1)
M_XSB EQU 5 ; DAX Start Block (XSB)
;------------------------------------------------------------------------
;
; EQUATES for SHI
;
;------------------------------------------------------------------------
; Register Addresses
M_HRX EQU $FFFF94 ; SHI Receive FIFO (HRX)
M_HTX EQU $FFFF93 ; SHI Transmit Register (HTX)
M_HSAR EQU $FFFF92 ; SHI I2C Slave Address Register (HSAR)
M_HCSR EQU $FFFF91 ; SHI Control/Status Register (HCSR)
M_HCKR EQU $FFFF90 ; SHI Clock Control Register (HCKR)