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DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor 4-1
4 Core Configuration
4.1 Introduction
This chapter contains DSP56300 core configuration information details specific to the DSP56366. These
include the following:
• Operating modes
• Bootstrap program
• Interrupt sources and priorities
• DMA request sources
•OMR
• PLL control register
• AA control registers
• JTAG BSR
For more information on specific registers or modules in the DSP56300 core, refer to the DSP56300 Family
Manual
(DSP56300FM).
4.2 Operating Mode Register (OMR)
Refer to the DSP56300 Family Manual, Freescale publication DSP56300FM for a description of the OMR
bits.