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DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
B-16 Freescale Semiconductor
M_S EQU 7 ; Scaling Bit
M_I0 EQU 8 ; Interupt Mask Bit 0
M_I1 EQU 9 ; Interupt Mask Bit 1
M_S0 EQU 10 ; Scaling Mode Bit 0
M_S1 EQU 11 ; Scaling Mode Bit 1
M_SC EQU 13 ; Sixteen_Bit Compatibility
M_DM EQU 14 ; Double Precision Multiply
M_LF EQU 15 ; DO-Loop Flag
M_FV EQU 16 ; DO-Forever Flag
M_SA EQU 17 ; Sixteen-Bit Arithmetic
M_CE EQU 19 ; Instruction Cache Enable
M_SM EQU 20 ; Arithmetic Saturation
M_RM EQU 21 ; Rounding Mode
M_CP EQU $c00000 ; mask for CORE-DMA priority bits in SR
M_CP0 EQU 22 ; bit 0 of priority bits in SR
M_CP1 EQU 23 ; bit 1 of priority bits in SR
; control and status bits in OMR
M_MA EQU 0 ; Operating Mode A
M_MB EQU 1 ; Operating Mode B
M_MC EQU 2 ; Operating Mode C
M_MD EQU 3 ; Operating Mode D
M_EBD EQU 4 ; External Bus Disable bit in OMR
M_SD EQU 6 ; Stop Delay
M_MS EQU 7 ;Memory Switch Mode
M_CDP EQU $300 ; mask for CORE-DMA priority bits in OMR
M_CDP0 EQU 8 ; bit 0 of priority bits in OMR Core DMA
M_CDP1 EQU 9 ; bit 1 of priority bits in OMR Core DMA