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DSP56366 24-Bit Digital Signal Processor, Rev. 4
Index-4 Freescale Semiconductor
R
reserved bits
in TCSR register
bits 3, 10, 14, 16–19, 22, 23 11
in TPCR 6
in TPLR 6
RESET 8
reverse-carry adder 5
S
SC register 6
Serial Host Interface 1, 12
Serial Host Interface (SHI) 10, 1
Serial Peripheral Interface Bus 10, 1
SHI 10, 1, 12, 1
Block Diagram 2
Clock Control Register—DSP Side 7
Clock Generator 2, 3
Control/Status Register—DSP Side 10
Data Size 11
Exception Priorities 5
HCKR
Clock Phase and Polarity Controls 7
Divider Modulus Select 9
Prescaler Rate Select 9
HCKR Filter Mode 9
HCSR
Bus Error Interrupt Enable 13
FIFO Enable Control 12
Host Request Enable 12
Idle 13
Master Mode 12
Serial Host Interface I
2
C/SPI Selection 11
Serial Host Interface Mode 11
SHI Enable 10
Host Receive Data FIFO—DSP Side 6
Host Transmit Data Register—DSP Side 6
HREQ
Function In SHI Slave Modes 12
HSAR
I
2
C Slave Address 7
Slave Address Register 6
I/O Shift Register 6
Input/Output Shift Register—Host Side 5
Internal Architecture 2
Internal Interrupt Priorities 5
Interrupt Vectors 5
Introduction 1
Operation During Stop 25
Programming Considerations 19
Programming Model 3
Programming Model—DSP Side 4
Programming Model—Host Side 3
Slave Address Register—DSP Side 6
SHI Noise Reduction Filter Mode 10
signal groupings 1
signals 1
Size register (SZ) 6
SP 6
SPI 10, 1
HCSR
Bus Error 16
Host Busy 16
Host Receive FIFO Full 15
Host Receive FIFO Not Empty 15
Host Receive Overrun Error 15
Host Transmit Data Empty 15
Host Transmit Underrun Error 14
Receive Interrupt Enable 13, 14
Master Mode 20
Slave Mode 19
SPI Data-To-Clock Timing 8
SPI Data-To-Clock Timing Diagram 8
SPI Mode 1
SR register 6
SRAM
interfacing 8
SS 6
Stack Counter register (SC) 6
Stack Pointer (SP) 6
Status Register (SR) 6
System Stack (SS) 6
SZ register 6
T
TAP 7