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Enhanced Serial Audio Interface
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
2-18 Freescale Semiconductor
SDO2/
SDO2_1
Output GPIO
disconnected
Serial Data Output 2 — When programmed as a transmitter, SDO2 is
used to transmit data from the TX2 serial transmit shift register
When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data
Output 2.
SDI3/
SDI3_1
Input Serial Data Input 3 — When programmed as a receiver, SDI3 is used
to receive serial data into the RX3 serial receive shift register.
When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Input
3.
PC9/PE9 Input, output, or
disconnected
Port C 9 — When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
When enabled for ESAI_1 GPIO, this is the Port E 9 signal.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
SDO1/
SDO1_1
Output GPIO
disconnected
Serial Data Output 1 — SDO1 is used to transmit data from the TX1
serial transmit shift register.
When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data
Output 1.
PC10/PE10 Input, output, or
disconnected
Port C 10 — When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
When enabled for ESAI_1 GPIO, this is the Port E 10 signal.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
SDO0/
SDO0_1
Output GPIO
disconnected
Serial Data Output 0 — SDO0 is used to transmit data from the TX0
serial transmit shift register.
When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data
Output 0.
PC11/
PE11
Input, output, or
disconnected
Port C 11 — When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
When enabled for ESAI_1 GPIO, this is the Port E 11 signal.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
Table 2-11 Enhanced Serial Audio Interface Signals (continued)
Signal Name Signal Type
State during
Reset
Signal Description