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DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor D-31
Figure D-16. ESAI Transmit Control Register
15 6 5 419 18 17 16 10 9 8 714 13 12 11
TE0
3210
TE2
23 22 21 20
TE1
TE3TE4TE5TSHFDTMOD0TFSLTFSRTEIETEDIETIETLIE
TFSR
Description
0
1
Word-length frame sync synchronous to
beginning of data word first slot
Word-length frame sync 1 clock before
beginning of data word first slot
Description
TMOD1
Network Mode
Normal mode
TEDIE Description
0
1
Transmit Even Slot Data Interrupt enabled
TIE
Description
0
1
Transmit Interrupt disabled
Transmit Interrupt enabled
TLIE Description
0
1
Transmit Last Slot Interrupt disabled
Transmit Last Slot Interrupt enabled
TEIE
Description
0
1
Transmit Exception Interrupt disabled
0
TSWS [0:4] Description
Defines slot and data word length
TFSL
Description
0
1
ESAI
TCR - ESAI Transmit Control Register
X: $FFFFB5 Reset: $000000
See 8.3.2.10 and table 8-5
TWA
Description
0
1
Data left aligned
Data right aligned
TSHFD Description
0
1
Data shifted out MSB first
Data shifted out LSB first
TE [0:5]
Transmitter disabled
Transmitter enabled
Description
0
1
Word length frame sync
1-bit clock period frame sync
Transmitter Normal Operation
Transmit Exception Interrupt enabled
Transmit Even Slot Data Interrupt disabled
TWATMOD1TSWS4
TSWS3 TSWS2 TSWS1
TSWS0
TMOD0
0
0
0
1
Network mode
Reserved
AC97
1
1
1
PADC
TPR
Transmitter Personal Reset
0
1
Description
Zero Padding disabled
PADC
Zero Padding enabled
0
1
TPR
Application:
D
ate:
Programmer:
*
0