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DSP56366 24-Bit Digital Signal Processor, Rev. 4
Freescale Semiconductor Index-1
Index
Numerics
5 V tolerance 1
A
adder
modulo 5
offset 5
reverse-carry 5
address bus 1
Address Generation Unit 5
addressing modes 5
AES/EBU 10, 1
AGU 5
B
barrel shifter 4
bus
external address 5
external data 5
bus control 1
buses
internal 6
C
Central Processing Unit (CPU) i
CLKGEN 7
Clock 4
clock 1
Clock divider 11
Clock Generator (CLKGEN) 7
CP-340 10, 1
CPHA and CPOL (HCKR Clock Phase and Polar-
ity Controls) 7
D
data ALU 4
registers 4
data bus 1
Data Output bit (DO) 10
DAX 1, 21
Block Transferred Interrupt Handling 11
Initiating A Transmit Session 10
Transmit Register Empty Interrupt Handling
10
DAX Audio Data register Empty (XADE) status
flag 8
DAX Audio Data Registers (XADRA/XADRB) 5
DAX Audio Data Shift Register (XADSR) 5
DAX biphase encoder 9
DAX Block transfer (XBLK) flag 8
DAX Channel A Channel status (XCA) bit 6
DAX Channel A User data (XUA) bit 6
DAX Channel A Validity (XVA) bit 5
DAX Channel B Channel Status (XCB) bit 6
DAX Channel B User Data (XUB) bit 6
DAX Channel B Validity (XVB) bit 6
DAX Clock input Select bits 7
DAX clock multiplexer 9
DAX clock selection 7
DAX Control Register (XCTR) 6
DAX internal architecture 4
DAX Interrupt Enable (XIEN) bit 7
DAX Non-Audio Data Buffer (XNADBUF) 6
DAX Operation During Stop 12
DAX Parity Generator (PRTYG) 9
DAX preamble generator 9
DAX Preamble sequence 9, 12
DAX Programming Considerations 10
DAX programming model 3
DAX Status Register (XSTR) 7
DAX Transmit Underrun error (XAUR) status flag
8
DI 10
Digital Audio Transmitter 1, 21
Digital Audio Transmitter (DAX) 10, 1
DIR 10
Divide Factor (DF) 7
DMA 6