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DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
B-14 Freescale Semiconductor
M_BRW0 EQU 2 ;Out of Page Wait States bit 0
M_BRW1 EQU 3 ; Out of Page Wait States bit 1
M_BPS EQU $300 ; DRAM Page Size Bits Mask (BPS0-BPS1)
M_BPS0 EQU 4 ; DRAM Page Size Bits 0
M_BPS1 EQU 5 ; DRAM Page Size Bits 1
M_BPLE EQU 11 ; Page Logic Enable
M_BME EQU 12 ; Mastership Enable
M_BRE EQU 13 ; Refresh Enable
M_BSTR EQU 14 ; Software Triggered Refresh
M_BRF EQU $7F8000 ; Refresh Rate Bits Mask (BRF0-BRF7)
M_BRF0 EQU 15 ; Refresh Rate Bit 0
M_BRF1 EQU 16 ; Refresh Rate Bit 1
M_BRF2 EQU 17 ; Refresh Rate Bit 2
M_BRF3 EQU 18 ; Refresh Rate Bit 3
M_BRF4 EQU 19 ; Refresh Rate Bit 4
M_BRF5 EQU 20 ; Refresh Rate Bit 5
M_BRF6 EQU 21 ; Refresh Rate Bit 6
M_BRF7 EQU 22 ; Refresh Rate Bit 7
M_BRP EQU 23 ; Refresh prescaler
; Address Attribute Registers
M_BAT EQU $3 ; External Access Type and Pin Definition Bits Mask (BAT0-BAT1)
M_BAT0 EQU 0 ; External Access Type and Pin Definition Bits 0
M_BAT1 EQU 1 ; External Access Type and Pin Definition Bits 1
M_BAAP EQU 2 ; Address Attribute Pin Polarity
M_BPEN EQU 3 ; Program Space Enable
M_BXEN EQU 4 ; X Data Space Enable
M_BYEN EQU 5 ; Y Data Space Enable