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DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
D-42 Freescale Semiconductor
Figure D-27. ESAI_1 Status Register
15 65419 18 17 16 10 9 8 714 13 12 11
IF0
3210
IF2
23 22 21 20
IF1
RFSRDF
Description
Description
0
1
Holds data sent from SCKR_1 pin.
SAISR_1 - ESAI_1 Status Register
Y: $FFFF93 Reset $000000
RFS Description
0
1
Receive frame sync did not occur
Description
Reserved
IF [0:2]
Reserved
ROE
Holds data sent from HCKR_1 pin.
Holds data sent from FSR_1 pin.
2
during word reception
Receive frame sync did occur
during word reception
ROE
Description
0
1
No receiver overrun error
Receiver overrun error
RDF
Description
0
1
Receive data register empty
Receive data register full
REDFRODF
TFS
TUETDE
TEDETODE
REDF
Description
0
1
Receive even-data register empty
Receive even-data register full
TODE
Description
0
1
Transmit odd-data register not empty
Transmit odd-data register empty
TFS Description
0
1
Transmit Frame sync did not occur during word transmission
Transmit frame sync occurred during word transmission
TUE Description
0
1
No transmit underrun error
Transmit underrun error
TDE Description
0
1
Transmit data registers not empty
Transmit data registers empty
TEDE Description
0
1
Transmit even-data registers not empty
Transmit even-data registers empty
Description
Reserved
RODF Description
0
1
Receive odd-data register empty
Receive odd-data register full
Application
:
Date:
Programmer:
Transmit odd-data register not empty
ESAI_1