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HDI08 Features
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
6-2 Freescale Semiconductor
— Bit addressing instructions (e.g. BCHG, BCLR, BSET, BTST, JCLR, JSCLR, JSET, JSSET)
simplify I/O service routines.
6.2.2 Interface - Host Side
• Sixteen signals are provided to support non-multiplexed or multiplexed buses:
— H0-H7/HAD0-HAD7
Host data bus (H7-H0) or host multiplexed address/data bus (HAD0-HAD7)
— HAS/HA0
Address strobe (HAS) or Host address line HA0
— HA8/HA1
Host address line HA8 or Host address line HA1
— HA9/HA2
Host address line HA9 or Host address line HA2
—HRW/HRD
Read/write select (HRW) or Read Strobe (HRD)
— HDS/HWR
Data Strobe (HDS) or Write Strobe (HWR)
—HCS/HA10
Host chip select (HCS) or Host address line HA10
— HOREQ/HTRQ
Host request (HOREQ) or Host transmit request (HTRQ)
— HACK/HRRQ
Host acknowledge (HACK) or Host receive request (HRRQ)
• Mapping:
— HDI08 registers are mapped into eight consecutive byte locations in the external host bus
address space.
— The HDI08 acts as a memory or IO-mapped peripheral for microprocessors, microcontrollers,
etc.
• Data Word:
—8-bit
• Transfer Modes:
— Mixed 8-bit, 16-bit and 24-bit data transfers
– DSP to Host
– Host to DSP
— Host Command
• Handshaking Protocols:
— Software polled
— Interrupt-driven (Interrupts are compatible with most processors, including the MC68000,
8051, HC11 and Hitachi H8).