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DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
B-30 Freescale Semiconductor
M_HORX EQU $FFFFC6 ; HOST Receive Register (HORX)
M_HBAR EQU $FFFFC5 ; HOST Base Address Register (HBAR)
M_HPCR EQU $FFFFC4 ; HOST Port Control Register (HPCR)
M_HSR EQU $FFFFC3 ; HOST Status Register (HSR)
M_HCR EQU $FFFFC2 ; HOST Control Register (HCR)
; HCR bits
M_HRIE EQU $0 ; HOST Receive interrupts Enable
M_HOTIE EQU $1 ; HOST Transmit Interrupt Enable
M_HCIE EQU $2 ; HOST Command Interrupt Enable
M_HF2 EQU $3 ; HOST Flag 2
M_HF3 EQU $4 ; HOST Flag 3
M_HODM0 EQU $5 ; HOST DMA Mode Control Bit 0
M_HODM1 EQU $6 ; HOST DMA Mode Control Bit 1
M_HODM2 EQU $7 ; HOST DMA Mode Control Bit 2
; HSR bits
M_HRDF EQU $0 ; HOST Receive Data Full
M_HOTDE EQU $1 ; HOST Receive Data Emptiy
M_HCP EQU $2 ; HOST Command Pending
M_HF0 EQU $3 ; HOST Flag 0
M_HF1 EQU $4 ; HOST Flag 1
M_DMA EQU $7 ; HOST DMA Status
; HPCR bits
M_HGEN EQU $0 ; HOST Port Enable
M_HA8EN EQU $1 ; HOST Address 8 Enable
M_HA9EN EQU $2 ; HOST Address 9 Enable