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AMP LIFIER
OUTPUT
TO
INTEGRATOR
R207
4
NOTE S,
I. JUMPER
IS REMOVED IF
SAMPLE/HOLD
OPTION
IS INSTALLED.
2.R429
LOCATED NEAR
REAR
OF
INSTRUIVENT
AND ACCESSIBLE THROUGH REAR
PANEL."
3.
WI
LOCATED
ON AIAI
4. VOLIAGES
wlTHlN
Al\,lPLlFlER MEASURED
WITH INPUT SHORTED,
IOV DC
RANGE,
SAMPLE
RATE TO HOLD.
5. IF SAMPLE/HOLD
IS
INSTALLED,
R5II IS
6. IF
THE U2 DATE CODE
IS PRECEDED BY
A
NUMEER SYMBOL
(*),AN
EXTERNAL
75N
RESTSToR,
PART NO.0698-3380
lS REQUIRED
IN SERIES
WITH U2
PIN 29.
$E?
O.lV
yt)""
X
CO GAIN L
4A?
16)
Z
ON
A2 PC LAYOUT
TH|S
PAGE,
lF
THE SAI\,IPLE,/
HOLD OPTION
IS INSTALLED,
JUMPERW9 IS
REI\,IOVED. THE SHIELDED CABLE
FROM SAMPLE/
HoLD
BoaRo
(A27)
coNNEcrs ro rHEsE
TERMINALS;
BLACK LEAD
TO LEFT TERMINAL'
WHITE
LEAD TO
RIGHT TERMINAL.
S.
EOOTSTRAP
CONNECTION
IS WHITE
WIRE FROM
A2U2 PIN I3.
$ CONNECTION
TO
O REF AND AC
OUT
IS
AS
FOLLOWS.O
REF.WHITE HEAT SHRINK LEAD.
AC OUT.BLACKHEAT
SHRINK
LEAD.
IO.IF
READING IN OHMS
IS LOW. CHECK K4O2
FOR SHORTING.
il. oEFECTTVE 0505-8,
lO A ll MAY CAUSE
OVERLOAD
SIGNAL OR
POLARIIY TURNOV€R
READINGS.
I2. IF
O.IV
RANGE IS NOISY
CHECK
R516.R517.Q5O9
a cR5r9.
IA
FET,.T'' MUS1
BE AT
-zOV
IN IHE
.,OFF.'
CONDITION
OR POLARITY IURNOVER AT FULL SCALE ANO
ZERO
VOLTS WtLL EXIST.
Figure
7-20. Schematic
Diagram,
DC Amplifier
Switching
Circuits,
Al
,
y'^2.
3
and
7-391740