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DELAY
MULTI
PLEX
ER
I5V
HOSE
HDSA
utl
LEVEL
TRAN
S
-
LATOR
STATE
STORAGE
LTON
L€<
IIOLD A H
TO
U2(6), A27
.sv
17
-fou
FROM
UgO
R9
(6)
t7K
TO ROM
ut4
+5v
-..l
ovL
MEMORY
R9(5)
r7K
LSHC LTON
R ro
(2)
t7K
I
I
STORAGE
+5V
MEMORY
STORAGE
+5V
-
(LEXN)
I5
EXTERNAL
TRIGGER
ENABLE
TO U7(9)
{
Hr HC)
INT IIOLD
COMMAND
H
TO
U7(3)
"u-l
Rro
(7)
t7K
(HDSA)
\
DELAY
sELEcr aHl
I
lro
u6(3,t3)
(HDSB)
I
DELAY
SELECT
BH
J
I
>(HMDB)
i
t-
I
I
I
Rto(6)
t7K
E/
HOLD
MODE
L
+5V
-]
r5v
{nrolat
Lov
?l7K
l']-,,",.,
To
Dc swtrcHtNc
I
r__+
".
>-
?6'
^Tr%r,..
i
I
5
HOLDBH I r
I.r,
Hn"oel
sauplezrolo
uoor
I
I
I
|
'l
lrru
lto
srr
aruar-ocl/
,l..,lyl
,
.[?.,f
4'6-ie-
*'^
-J
toM
ue
(tst
|
"-"
)
--,*J
1g
Figure
7-35.
Schematic
Diagam,
Sample/Hold
Logic
Circuits, A2g.
74917-70