LS HC
TRANSFER
AND
ZERO
DETECT
+5V
(HAZD)
ANALOG
ZERO
DETECT
FROM
U203
(7)
HMQC
(
LTXF)
rnarusrER
L 6
ro
u?,4
(HZDT)
ZERO OETECT
H
TO
ut9fl)
OUALI FIER
ENABLE
SIGNALS
^r
iöi,liisliä)31,"q
3Yä1.^.dP
(HTC32)
TIME COUNT
32
(
LCOV)
CLOCK
OVERLOAD
L
FROM
UI6(9)
ALL
IC's
Vl€WED
FROM
TOp
ut8
AND
-
OR
INVERT
GATE
INPUT
POLAR
ITY
STORAG
E
IIME
COUNT
32
(HTC32)
(HTFE
)
TANSFER
ENABLE
H
FROM
U9
(2I)
3
l8'd',tshäl'"
5'8
3,9,
t2)
rc
R20
|
i
_l
*""^;'
Figure
7-24.
Schematic
Diagram,
Main
Logic,
Al.
7471.748