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ADDDP Add Two Double-Precision Floating-Point Values
3-58 Instruction Set SPRU733
Pipeline
Stage
E1 E2 E3 E4 E5 E6 E7
Read src1_l
src2_l
src1_h
src2_h
Written dst_l dst_h
Unit in use
.L or .S .L or .S
For the C67x CPU, if dst is used as the source for the ADDDP, CMPEQDP,
CMPLTDP, CMPGTDP, MPYDP, or SUBDP instruction, the number of delay
slots can be reduced by one, because these instructions read the lower word
of the DP source one cycle before the upper word of the DP source.
For the C67x+ CPU, the low half of the result is written out one cycle earlier
than the high half. If dst is used as the source for the ADDDP, CMPEQDP,
CMPLTDP, CMPGTDP, MPYDP, MPYSPDP, MPYSP2DP, or SUBDP
instruction, the number of delay slots can be reduced by one, because these
instructions read the lower word of the DP source one cycle before the upper
word of the DP source.
Instruction Type ADDDP/SUBDP
Delay Slots 6
Functional Unit
Latency
2
See Also ADD, ADDSP, ADDU, SUBDP
Example
ADDDP .L1X B1:B0,A3:A2,A5:A4
Before instruction 7 cycles after instruction
B1:B0
4021 3333h
3333 3333h 8.6 B1:B0 4021 3333h 4021 3333h 8.6
A3:A2 C004 0000h 0000 0000h −2.5 A3:A2 C004 0000h 0000 0000h −2.5
A5:A4 XXXX XXXXh XXXX XXXXh A5:A4 4018 6666h 6666 6666h 6.1
Pipeline