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Multiply Two Single-Precision Floating-Point Values for Double-Precision Result (C67x+ CPU) MPYSP2DP
3-171 Instruction SetSPRU733
Pipeline
Stage
E1 E2 E3 E4 E5
Read src1
src2
Written dst_l dst_h
Unit in use
.M
The low half of the result is written out one cycle earlier than the high half. If
dst is used as the source for the ADDDP, CMPEQDP, CMPLTDP, CMPGTDP,
MPYDP, MPYSPDP, MPYSP2DP, or SUBDP instruction, the number of delay
slots can be reduced by one, because these instructions read the lower word
of the DP source one cycle before the upper word of the DP source.
Instruction Type 5-cycle
Delay Slots 4
Functional Unit
Latency
2
See Also MPY, MPYDP, MPYSP, MPYSPDP
Pipeline