Texas Instruments TMS320C67X/C67X+ DSP Car Speaker User Manual


 
Pipeline Operation Overview
4-5PipelineSPRU733
4.1.3 Execute
The execute portion of the pipeline is subdivided into ten phases (E1E10),
as compared to the five phases in a fixed-point pipeline. Different types of
instructions require different numbers of these phases to complete their
execution. These phases of the pipeline play an important role in your
understanding the device state at CPU cycle boundaries. The execution of dif-
ferent types of instructions in the pipeline is described in section 4.2, Pipeline
Execution of Instruction Types. Figure 44(a) shows the execute phases of
the pipeline in sequential order from left to right. Figure 44(b) shows the
portion of the functional block diagram in which execution occurs.
Figure 44. Execute Phases of the Pipeline
E4E3E2E1
E5
(a)
(b)
Register file A Register file B
Data 2Data 1 3232
3232
(byte addressable)
Internal data memory
Data address 2Data address 1
98
76543210
16 1616
16
Data memory interface control
32
.L1
SADD
.S1
B
.M1
SMPY
01354 26871012 11 91415 13
0123456789101112131415
.L2
SADD
.S2
SUB
SMPYH
.M2
Execute
E1
.D1
STH
.D2
STH
E9E8E7E6
E10