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Resource Constraints
3-23Instruction SetSPRU733
3.7.5 Constraints on Long (40-Bit) Data
Because the .S and .L units share a read register port for long source operands
and a write register port for long results, only one long result may be issued
per register file in an execute packet. All instructions with a long result on the
.S and .L units have zero delay slots. See section 2.2 for the order for long
pairs.
The following execute packet is invalid:
ADD.L1 A5:A4,A1,A3:A2 ; \ Two long writes
|| SHL.S1 A8,A9,A7:A6 ; / on A register file
The following execute packet is valid:
ADD.L1 A5:A4,A1,A3:A2 ; \ One long write for
|| SHL.S2 B8,B9,B7:B6 ; / each register file
Because the .L and .S units share their long read port with the store port,
operations that read a long value cannot be issued on the .L and/or .S units
in the same execute packet as a store.
The following execute packet is invalid:
ADD.L1 A5:A4,A1,A3:A2 ; \ Long read operation and a
|| STW .D1 A8,*A9 ; / store
The following execute packet is valid:
ADD.L1 A4, A1, A3:A2 ; \ No long read with
|| STW.D1 A8,*A9 ; / the store
On the C67x DSP, doubleword load instructions conflict with long results from
the .S units. All stores conflict with a long source on the .S unit. The following
execute packet is invalid, because the .D unit store on the T1 path conflicts with
the long source on the .S1 unit:
ADD .S1 A1,A5:A4, A3:A2 ; \ Long source on .S unit and a store
|| STW .D1T1 A8,*A9 ; / on the T1 path of the .D unit
The following code sequence is invalid:
LDDW .D1T1 *A16,A11:A10 ; \ Double word load written to
; A11:A10 on .D1
NOP 3 ; conflicts after 3 cycles
SHL .S1 A8,A9,A7:A6 ; / with write to A7:A6 on .S1
The following execute packets are valid:
ADD .L1 A1,A5:A4,A3:A2 ; \ One long write for
|| SHL .S2 B8,B9,B7:B6 ; / each register file
ADD .L1 A4, A1, A3:A2 ; \ No long read with
|| STW .D1T1 A8,*A9 ; / the store on T1 path of .D1