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xiv SPRU733Tables
Tables
1−1 Typical Applications for the TMS320 DSPs 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−1 40-Bit/64-Bit Register Pairs 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 Functional Units and Operations Performed 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−3 Control Registers 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−4 Register Addresses for Accessing the Control Registers 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . .
2−5 Addressing Mode Register (AMR) Field Descriptions 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6 Block Size Calculations 2-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−7 Control Status Register (CSR) Field Descriptions 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−8 Interrupt Clear Register (ICR) Field Descriptions 2-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−9 Interrupt Enable Register (IER) Field Descriptions 2-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−10 Interrupt Flag Register (IFR) Field Descriptions 2-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−11 Interrupt Set Register (ISR) Field Descriptions 2-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−12 Interrupt Service Table Pointer Register (ISTP) Field Descriptions 2-21. . . . . . . . . . . . . . . . . .
2−13 Control Register File Extensions 2-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−14 Floating-Point Adder Configuration Register (FADCR) Field Descriptions 2-24. . . . . . . . . . . .
2−15 Floating-Point Auxiliary Configuration Register (FAUCR) Field Descriptions 2-27. . . . . . . . . .
2−16 Floating-Point Multiplier Configuration Register (FMCR) Field Descriptions 2-31. . . . . . . . . .
3−1 Instruction Operation and Execution Notations 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2 Instruction Syntax and Opcode Notations 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3 IEEE Floating-Point Notations 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4 Special Single-Precision Values 3-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5 Hexadecimal and Decimal Representation for Selected Single-Precision Values 3-12. . . . . .
3−6 Special Double-Precision Values 3-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−7 Hexadecimal and Decimal Representation for Selected Double-Precision Values 3-13. . . . .
3−8 Delay Slot and Functional Unit Latency 3-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
−9 Registers That Can Be Tested by Conditional Operations 3-19. . . . . . . . . . . . . . . . . . . . . . . . .
3−10 Indirect Address Generation for Load/Store 3-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−11 Address Generator Options for Load/Store 3-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−12 Relationships Between Operands, Operand Size, Signed/Unsigned,
Functional Units, and Opfields for Example Instruction (ADD) 3-36. . . . . . . . . . . . . . . . . . . . . .
3−13 Program Counter Values for Example Branch Using a Displacement 3-70. . . . . . . . . . . . . . . .
3−14 Program Counter Values for Example Branch Using a Register 3-72. . . . . . . . . . . . . . . . . . . .
3−15 Program Counter Values for B IRP Instruction 3-74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−16 Program Counter Values for B NRP Instruction 3-76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−17 Data Types Supported by LDB(U) Instruction 3-123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−18 Data Types Supported by LDB(U) Instruction (15-Bit Offset) 3-126. . . . . . . . . . . . . . . . . . . . . .