Texas Instruments TMS320C67X/C67X+ DSP Car Speaker User Manual


 
Pipeline Operation Overview
4-3PipelineSPRU733
Figure 42. Fetch Phases of the Pipeline
PRPWPSPG
PW
Memory
PS
PR
PG
Registers
units
Functional
(a)
(b)
CPU
PR
PW
PS
PG
256
MVKLDWLDWSHLADDMVKLDWLDW
NOP
MVK
MV
B
SADD
SMPYH
SADD
SHR
SMPY
SHR
SMPYH
LDW
LDW
LDW
LDW
MVKBSMPYSMPYHMVMVKLHLDWLDW
Fetch
SMPYH
Decode
(c)
4.1.2 Decode
The decode phases of the pipeline are:
DP: Instruction dispatch
DC: Instruction decode
In the DP phase of the pipeline, the fetch packets are split into execute pack-
ets. Execute packets consist of one instruction or from two to eight parallel
instructions. During the DP phase, the instructions in an execute packet are
assigned to the appropriate functional units. In the DC phase, the the source
registers, destination registers, and associated paths are decoded for the
execution of the instructions in the functional units.