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General-Purpose Register Files
CPU Data Paths and Control2-4 SPRU733
Table 2−1. 40-Bit/64-Bit Register Pairs
Register Files
A B
Devices
A1:A0 B1:B0 C67x DSP
A3:A2 B3:B2
A5:A4 B5:B4
A7:A6 B7:B6
A9:A8 B9:B8
A11:A10 B11:B10
A13:A12 B13:B12
A15:A14 B15:B14
A17:A16 B17:B16 C67x+ DSP only
A19:A18 B19:B18
A21:A20 B21:B20
A23:A22 B23:B22
A25:A24 B25:B24
A27:A26 B27:B26
A29:A28 B29:B28
A31:A30 B31:B30
Figure 2−2. Storage Scheme for 40-Bit Data in a Register Pair
31 0 31 0
Odd register Even register
39 32 31 0
Zero-filled
40-bit data
39 32 31 0
40-bit data
Odd register Even register
Read from registers
Write to registers
Ignored
78