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5-1InterruptsSPRU733
9
Interrupts
This chapter describes CPU interrupts, including reset and the nonmaskable
interrupt (NMI). It details the related CPU control registers and their functions
in controlling interrupts. It also describes interrupt processing, the method the
CPU uses to detect automatically the presence of interrupts and divert
program execution flow to your interrupt service code. Finally, the chapter
describes the programming implications of interrupts.
Topic Page
5.1 Overview 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 Globally Enabling and Disabling Interrupts 5-11. . . . . . . . . . . . . . . . . . . . .
5.3 Individual Interrupt Control 5-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 Interrupt Detection and Processing 5-16. . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 Performance Considerations 5-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6 Programming Considerations 5-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 5